1. Technical Field
The present invention relates to a test apparatus and a measurement circuit. More particularly, the present invention relates to a test apparatus for testing a device under test and to a measurement circuit for measuring a signal under measurement.
2. Related Art
A known test apparatus for testing a device under test measures a signal under measurement which is output from the device under test, and judges whether the device under test passes or fails a test based on the result of the measurement. For example, a known apparatus measures the logic pattern of the signal under measurement and judges whether the measured logic pattern matches an expected value pattern, to judge whether the device under test passes or fails the test.
The logic pattern of the signal under measurement can be detected by sampling the signal under measurement with the use of a sampling clock which is in synchronization with the bit rate of the signal under measurement. Therefore, it is preferable that the timings of the edge positions and bit boundaries of the signal under measurement are accurately controlled.
Nevertheless, the timings of the edge positions and bit boundaries of the signal under measurement are displaced from corresponding ideal timings depending on the rising time Tr and the falling time Tf of the signal under measurement. When the signal under measurement is a differential signal, the crossing point of the differential signal is displaced from a corresponding ideal crossing point depending on such factors as the skew between the positive signal and the negative signal.
A known technique to compensate such displacement of the crossing point is disclosed in, for example, Unexamined Japanese Patent Application Publication No. 2001-60854. According to this technique, the timing of the crossing point is adjusted by shifting the static voltage level of one of the positive and negative signals.
FIG. 6 illustrates a differential signal. As described above, the timing of the crossing point of an actually output waveform is displaced from the timing of the crossing point of an ideal waveform. To remove the displacement, one of the positive and negative signals is shifted in the direction along the voltage axis. In this way, the timing of the crossing point can be compensated as indicated by the shifted waveform shown in FIG. 6.
However, when one of the positive and negative signals is shifted in the direction along the voltage axis, the difference in level between the positive and negative signals increases in correspondence with the amount by which one of the positive and negative signals is shifted. Therefore, the timing of the crossing point may not be sufficiently compensated, for example, when the circuit which receives the differential signal can only withstand a low voltage.